Sept 2026publication
[C5] 256–316 GHz frequency quadrupler accepted by ESSERC 2026
W. Wu, …, X. Wang, et al., “A 256-316-GHz Frequency Quadrupler…,” ESSERC 2026 (Accepted as Lecture).
Timeline
All publications, research interests, and career milestones from the CV.
Sept 2026publication
[C4] All-digital current-mode IVR accepted by ESSERC 2026
X. Men, R. Chen, …, X. Wang, et al., “A 280 MHz All-Digital Current-Mode IVR…,” ESSERC 2026 (Accepted as Lecture).
Sept 2026publication
[C3] Autonomous current-booster chiplet accepted by ESSERC 2026
R. Chen, X. Men, …, X. Wang, et al., “An Autonomous Computational Current-Booster Chiplet for Fast Droop Mitigation…,” ESSERC 2026 (Accepted as Lecture).
Sept 2026publication
[C2] Resonant-tank VPD converter accepted by IEEE ESSERC 2026 (Lecture)
X. Wang et al., “A 96.6%-Peak-Efficiency 4.63-A/mm³ Resonant-Tank Converter with RDL Trace Inductor and Trajectory Control for Vertical Power Delivery,” ESSERC 2026 (Accepted as Lecture).
Sept 2026publication
[C1] Mobius accepted by IEEE ESSERC 2026 (Lecture)
X. Wang et al., “Mobius: A 12V-to-1V Charge-Cross-Converging Converter Ring with Monolithic Handshake Driving for Next-Generation AI Server,” ESSERC 2026 (Accepted as Lecture).
Aug 2026publication
[J3] First-author paper published in IEEE JSSC (Early Access)
X. Wang et al., “A 6-A 93.8%-Peak-Efficiency 5V-to-Sub-1V Segment-Interlaced SC-Parallel-Inductor Converter Featuring Inherently Balanced Ganging for Wafer-Scale Computing System,” IEEE JSSC (Early Access), Aug. 2026.
Jul 2026service
Session Chair — IEEE COMPEL 2026
Serving as Session Chair at the IEEE Workshop on Control and Modeling for Power Electronics (COMPEL) 2026.
Jul 2026publication
[C7] Hybrid SC algebraic synthesis accepted by IEEE COMPEL 2026 (Poster)
X. Wang et al., “Algebraic Synthesis for A Family of Inherently Balanced Multi-Phase Hybrid Switched-Capacitor Converters…,” COMPEL 2026 (Accepted as Poster).
Chip Gallery
Technical appendix figures — JSSC [J2, J3], ESSERC [C1, C2], CICC [C8], and TCAS-I [J1].
SCSL
Figure 1 — JSSC 2026
Switched-Capacitor-Stack-Inductor Volumetric IVR with Auxiliary-Assisted Gain Boosting for High-Density PoL Applications [J2].
JSSCChip Gallery
SI-SCPL
Figure 2 — JSSC 2026
6-A 93.8%-Peak-Efficiency Segment-Interlaced SC-Parallel-Inductor Converter for Wafer-Scale Computing [J3].
JSSCChip Gallery
ReLA
Figure 3 — ESSERC 2026
96.6%-Peak-Efficiency Resonant-Tank Converter with RDL Trace Inductor and Trajectory Control for Vertical Power Delivery [C2].
ESSERC 2026Chip Gallery
Mobius
Figure 4 — ESSERC 2026
Mobius: A 12V-to-1V Charge-Cross-Converging Converter Ring with Monolithic Handshake Driving for Next-Generation AI Server [C1].
ESSERC 2026Chip Gallery
Unicorn
Figure 5 — CICC 2026
Unicorn: A Unified Clock-and-Power SoC with RL-Adapted Digital SIMO Control and In-TRO Frequency Boosting for Edge Computing [C8].
CICC 2026Chip Gallery
UVFR
Figure 6 — TCAS-I 2023
A Self-Clocked and Variation-Tolerant Unified Voltage-and-Frequency Regulator for In-Order Executed Digital Loads [J1].
TCAS-IChip Gallery
Photos
Conference milestones and travel albums — The Sun Never Sets, Echoes of Blue Hours, Wanderlust & Pathways.
IEEE COMPEL 2026
Cambridge, UK · July 2026
At the IEEE Workshop on Control and Modeling for Power Electronics (COMPEL) in Cambridge — presenting power-electronics research and serving as Session Chair.
COMPELCambridgeConference
IEEE CICC 2026
Seattle, WA, USA · April 2026
At the IEEE Custom Integrated Circuits Conference (CICC) in Seattle — showcasing the Unicorn unified clock-and-power SoC and connecting with the IC design community.
CICCSeattleConference
Ph.D. Defense
HKUST, Hong Kong · Dec 2022
Doctoral dissertation defense on the eve of Christmas 2022 at the Hong Kong University of Science and Technology — IR-Drop- and Timing-Aware Power Management Techniques for Microprocessors (supervisor: Prof. Wing-Hung Ki).
Ph.D.HKUSTMilestone
Research Interests
Core research line: Integrated Power Delivery for 2.5D/3D Heterogeneous Systems — Vertical Power Delivery (VPD), high-density PMIC & SiP, and package-integrated multiphase IVRs for AI accelerators and data centers.
Pillar 1
Integrated Power Delivery for 2.5D/3D Heterogeneous Systems
Vertical Power Delivery (VPD) & SiP, package-integrated multiphase IVRs, and holistic circuit-package co-design for AI accelerators and data centers.
View details & related work →
Research Focus: Architectures for chiplet systems including high-density Intermediate Bus Converters (IBC) and Point-of-Load (PoL) regulators; multiphase package-integrated regulators and flip-chip PMICs; systematic optimization framework pushing the Pareto frontier of volumetric power density and system efficiency.
Key Contributions:
- Independently spearheaded end-to-end design, tape-out, and validation of 7 flip-chip PMICs; co-designed and verified 4 additional PMICs with 100% silicon success rate.
- Established end-to-end design methodology for flip-chip PMICs and SiP integration targeting reduced iteration cycles for multi-chiplet power delivery networks.
- First-authored 3 flagship conference papers at IEEE CICC 2026 and IEEE ESSERC 2026; 2 regular papers in IEEE JSSC on advanced IVR architectures.
Related Publications:
- ESSERC 2026 — Mobius 12V-to-1V converter ring for AI servers [C1]
- ESSERC 2026 — Resonant-tank converter for vertical power delivery [C2]
- JSSC — SCSL volumetric IVR with auxiliary-assisted gain boosting [J2]
- JSSC — Segment-interlaced SC-parallel-inductor converter [J3]
Pillar 2
High-Efficiency Power Conversion & Intelligent Mixed-Signal Control
Hybrid/resonant SC topologies, learning-based control, and SIMO cross-regulation mitigation for compact high-density systems.
View details & related work →
Research Focus: Advanced Hybrid/Resonant Switched-Capacitor topologies for soft-switching high-density regulation; circuit-level model/learning-based control and transient-aware algorithms; Single-Inductor Multiple-Output (SIMO) architectures with active cross-regulation suppression.
Key Contributions:
- Pioneered novel Hybrid/Resonant SC topologies and trajectory-based soft-switching control pushing Pareto frontiers of volumetric power density.
- Chip implementation of lightweight learning algorithm into SIMO converter control for dynamic real-time cross-regulation mitigation.
- Published 5 first-authored papers in IEEE APEC and IEEE COMPEL.
Related Publications:
- APEC 2026 — X-ReLA ReSC with 98.2% peak efficiency [C10]
- APEC 2026 — Multi-resonant cascaded SC converter [C11]
- COMPEL 2026 — GaN buck state-plane analysis; hybrid SC algebraic synthesis [C6, C7]
- APEC 2025 — Time-optimal control for unordered SIDO converter [C18]
Pillar 3
Clocking-Power Co-Design, Dynamic Scaling & Resilient Architectures
Unified power-clock regulation, DVFS/MEP for ULP edge devices, IMC power-timing co-design, and circuit-level side-channel countermeasures.
View details & related work →
Research Focus: Instruction-driven adaptive clocking, Unified Voltage-and-Frequency Regulators (UVFRs), and Minimum Energy Point (MEP) tracking; power-timing co-design for In-Memory Computing, voltage-stacked delivery, and WPT; integrated countermeasures for Power Side-Channel Attack.
Key Contributions:
- Spearheaded instruction-driven proactive clocking and adaptive power management for energy savings and ultra-dynamic transient response.
- Led design of unified voltage-and-frequency regulators bridging digital clocking and analog power delivery.
- Published 4 first-authored papers including IEEE TCAS-I and IEEE A-SSCC 2022.
Related Publications:
- CICC 2026 — Unicorn: Unified Clock-and-Power SoC [C8]
- IEEE TCAS-I 2023 — Self-clocked UVFR [J1]
- A-SSCC 2022 — Self-clocked TDC-based unified clock and voltage regulator [C24]
Selected Academic Achievements
- Pillar 1 — Proven tape-out track record: 7 independent + 4 co-designed flip-chip PMICs with 100% silicon success; end-to-end Flip-chip PMIC & SiP methodology; 3 first-authored CICC/ESSERC 2026 papers and 2 first-authored IEEE JSSC papers on IVR.
- Pillar 2 — Architectural breakthroughs in Hybrid/Resonant SC topologies and trajectory-based soft-switching; lightweight learning algorithm in SIMO control for real-time cross-regulation mitigation; 5 first-authored APEC/COMPEL papers.
- Pillar 3 — Instruction-driven proactive clocking and adaptive power management; unified voltage-and-frequency regulators (UVFR); 4 first-authored papers including IEEE TCAS-I and IEEE A-SSCC 2022.
Publications
Complete list from CV — conference papers [C1]–[C26] and journal papers [J1]–[J3].
[J3] A 6-A 93.8%-Peak-Efficiency 5V-to-Sub-1V Segment-Interlaced SC-Parallel-Inductor Converter Featuring Inherently Balanced Ganging for Wafer-Scale Computing System
Aug 2026 · Early AccessX. Wang, X. Men, Z. Liu, W.-H. Ki, J. Wei, Y. Wang, and X. Liu
IEEE Journal of Solid-State Circuits (JSSC) · First author
[J2] A 0.73 A/mm³ Switched-Capacitor-Stack-Inductor Volumetric Integrated Voltage Regulator with Auxiliary-Assisted Gain Boosting for High-Density PoL Applications
Jul 2026 · Early AccessX. Wang, R. Chen, H. Wang, Y. Liu, W.-H. Ki, Y. Wang, and X. Liu
IEEE Journal of Solid-State Circuits (JSSC) · First author
[C1] Mobius: A 12V-to-1V Charge-Cross-Converging Converter Ring with Monolithic Handshake Driving for Next-Generation AI Server
Sept 2026 · Accepted as LectureX. Wang, Z. Liu, H. Wang, T. Min, W.-H. Ki, Y. Wang, and X. Liu
IEEE ESSERC · First author
[C2] A 96.6%-Peak-Efficiency 4.63-A/mm³-Peak-Density Resonant-Tank Converter with RDL Trace Inductor and Trajectory Control for Vertical Power Delivery
Sept 2026 · Accepted as LectureX. Wang, Z. Liu, Y. Yao, W. Wu, J. Jiang, Y. Wang, and X. Liu
IEEE ESSERC · First author
[C3] An Autonomous Computational Current-Booster Chiplet for Fast Droop Mitigation and Universal Compatibility in 3D-IC Vertical Power Delivery
Sept 2026 · Accepted as LectureR. Chen, X. Men, Z. Liu, Y. Wang, X. Wang, J. Xu, J. Yu, R. Chen, J. Wei, et al.
IEEE ESSERC
[C4] A 280 MHz All-Digital Current-Mode IVR with Dual-Observation Current Telemetry and Kalman Filter-Based Fusion for Scalable Ganged Systems
Sept 2026 · Accepted as LectureX. Men, R. Chen, Y. Wang, B. Zhang, Z. Liu, H. Liu, X. Wang, Z. Zhang, J. Yu, et al.
IEEE ESSERC
[C5] A 256-316-GHz Frequency Quadrupler with Polyphase Continuous Harmonic Tuning and Power Combining Network in 65-nm CMOS
Sept 2026 · Accepted as LectureW. Wu, X. Bao, J. Wang, S. Chen, X. Wang, X. Liu, Y. Wang, and L. Zhang
IEEE ESSERC
[C6] Geometrical State-Plane Analysis of GaN-Based Buck Converters with Auxiliary-Assisted Zero-Voltage Switching
Jul 2026 · Accepted as LectureX. Wang, W.-H. Ki, Y. Liu, J. Wei, Y. Wang, and X. Liu
IEEE COMPEL · First author
[C7] Algebraic Synthesis for A Family of Inherently Balanced Multi-Phase Hybrid Switched-Capacitor Converters Leveraging Cyclic Symmetry
Jul 2026 · Accepted as PosterX. Wang, W.-H. Ki, Y. Yao, Y. Zhong, Y. Wang, and X. Liu
IEEE COMPEL · First author
[C15] A Triple-Path Resonant-Tracked Voltage Regulator with Package Inductor for System-on-Wafer Vertical Power Delivery
May 2026 · PublishedR. Chen, Z. Liu, X. Men, X. Wang, Y. Wang, X. Liu
IEEE ISPSD
[C8] Unicorn: A Unified Clock-and-Power SoC with RL-Adapted Digital SIMO Control and In-TRO Frequency Boosting for Edge Computing
Apr 2026 · PublishedX. Wang, H. Wang, X. Men, R. Chen, J. Jiang, Y. Wang, and X. Liu
IEEE CICC · First author
[C9] A 200kHz Self-Powered Isolated Gate Driver for SiC and IGBT with Synchronous Regulation of 62.6% Efficiency
Apr 2026 · PublishedY. Liu, Y. Yao, G. Zhu, D. Pan, C. Hua, X. Wang, W. Xu, Z. Liu, W. Xu, Y. Li, W.-H. Ki, L. Cheng, and Z. Zhu
IEEE CICC
[C10] X-ReLA: a Family of Stacked-Ladder Charge-Cross-Converging ReSC with 98.2% Peak Efficiency Featuring Wide Voltage Conversion Ratio and Always Reduced Inductor Current
Mar 2026 · PublishedX. Wang, H. Wang, Z. Liu, Y. Yao, Y. Liu, W.-H. Ki, J. Wei, Y. Wang, and X. Liu
IEEE APEC · First author
[C11] A Multi-Resonant Cascaded Series-Parallel Switched-Capacitor Converter Featuring Continuously Scalable Conversion Ratio
Mar 2026 · PublishedX. Wang, H. Wang, Z. Liu, Y. Yao, Y. Liu, W.-H. Ki, J. Wei, Y. Wang, and X. Liu
IEEE APEC · First author
[C12] A 30-60V Input 6V Output Regulated Resonant SC Converter with Unified Hard-Soft Switching Control Achieving 100A and 1339W/in³ for High-Performance Computing
Mar 2026 · PublishedH. Wang, Z. Liu, J. Xu, X. Wang, Y. Liu, X. Li, J. Cui, Y. Wang, X. Liu
IEEE APEC
[C13] Current–Temperature–Resistance Modeling and Conversion Loss Sharing Methodology for Optimized Efficiency and Thermal Distribution in Large-Scale HPC Power Delivery Networks
Mar 2026 · PublishedH. Wang, Z. Liu, J. Xu, X. Wang, M. Xiong, Y. Liu, X. Li, J. Cui, Y. Wang, X. Liu
IEEE APEC
[C14] A 1295W/in³ 160A Quad-Phase VPD Module with Flexible Ganging and Multiphysics Optimization for Large-Scale HPC Systems
Mar 2026 · PublishedH. Wang, Z. Liu, J. Xu, X. Wang, M. Xiong, Y. Liu, X. Li, J. Cui, Y. Wang, X. Liu
IEEE APEC
[C21] A Discontinuously Resonant Operation for Continuously-Scalable-Conversion-Ratio Switched Capacitor Converter with Enhanced Power Efficiency and Output Capability
Oct 2025 · PublishedH. Zhang, C. Wang, X. Liu, X. Wang, R. Chen, X. Men, F. Wang, and Y. Wang
IEEE APCCAS
[C16] A 10W 3.8-5V Input IVR Chiplet with 93%-Peak-Efficiency and 3.2A/mm² Density Featuring Wide Load Range and Adaptive Ganging for 2.5D/3D Vertical Power Delivery
Jun 2025 · PublishedX. Sun, X. Wang, R. Chen, X. Men, J. Jiang, Y. Wang, and X. Liu
IEEE Symposium on VLSI Technology and Circuits
[C22] A Capacitorless Fully Synthesizable Digital-LDO Using Scalable APR-Friendly Power MOS Cell with 13.71A/mm² Current Density
Jun 2025 · PublishedY. Wang, X. Wang, B. Zhang, R. Chen, X. Men and X. Liu
IEEE EDSSC
[C17] E-NPU: A 34~126nJ/Class Event-Driven Adaptive Neural SoC with Signal-Dynamics-Aware Feature Clustering and Multi-Model In-Memory Inference/Training for Personalized Medical Wearables
Apr 2025 · PublishedF. Tian, J. Chen, K. Shao, Z. Liu, J. Zheng, H. Wu, C. Fang, X. Wang, Z. Shen, P. Dong, Y. Yao, X. Wang, J. Yang, M. Sawan, C.-Y. Tsui, and K.-T. Cheng
IEEE CICC
[C18] Concurrent Charge Distribution and Time-Optimal Control for Unordered Single-Inductor Dual-Output Converter
Mar 2025 · PublishedX. Wang, H. Wang, Y. Liu, Y. Wang, B. Zhang, H. Liu, Y. Wang, and X. Liu
IEEE APEC · First author
[C19] A 660W, 96% Efficiency 3D Heterogeneously Integrated Digital DC/DC Power Module for Vertical Power Delivery
Mar 2025 · PublishedH. Wang, X. Wang, Y. Wang, and X. Liu
IEEE APEC
[C20] Evaluation Index-Based Multiphysics Coupling Model and Analysis Methodology for High-Reliable Power Supply Module
Mar 2025 · PublishedH. Wang, X. Wang, Y. Wang, and X. Liu
IEEE APEC
[C23] A 92%-Efficiency 0.828μs Settling Time FC5L Voltage Regulator Featuring Time-Domain Charge Balancing & Flying Capacitor Self-Switching for Wide Dynamic Range & Fast Transient Chiplet Applications
Apr 2024 · PublishedX. Sun, J. Yu, X. Wang, J. Wei, J. Jiang, C. Zhan, Y. Wang, and X. Liu
IEEE CICC
[J1] A Self-Clocked and Variation-Tolerant Unified Voltage-and-Frequency Regulator for In-Order Executed Digital Loads
Nov 2023 · PublishedX. Wang, X. Liu, and W.-H. Ki
IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I) · First author
[C24] A Self-Clocked TDC-Based Unified Clock and Voltage Regulator with Replica Frequency-Locked Loop and Hysteresis Switching in 65nm CMOS
Nov 2022 · PublishedX. Wang, W.-H. Ki, and P. K. T. Mok
IEEE A-SSCC · First author
[C26] A 65-nm Clock-Domain-Crossing Controller for Digital LDO Regulator with 1.7-ns Response Time
Nov 2022 · PublishedX. Wang and W.-H. Ki
IEEE APCCAS · First author
[C25] Partitioning Scheme and Performance Analysis of Distributed Digital Low-Dropout Regulators in SoC
Jun 2022 · PublishedX. Wang and W.-H. Ki
IEEE ISCAS · First author
Contact
Email: xwangef@connect.ust.hk
Phone: +86 15151856366
Office: CYT Building, The Hong Kong University of Science and Technology, Hong Kong SAR
Open to faculty positions and collaborative research on mixed-signal power management ICs, 3D ICs, and emerging power delivery solutions.